Error:Top-level design entity "Verilog1" is undefined

题目

Error:Top-level design entity "Verilog1" is undefined
最近在玩QUARTUS
本人用的时VERILOG HDL硬件描述语言!
初学者,见谅!

答案

Most likely you named the project something different than your top-level entity/module/filename. (Type depends on source, where entity=VHDL, module=Verilog, and filename.bdf=schematic). To tell Quart...