Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (On the board ) Violation Via (28.90708mm,0.57355m

题目

Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (On the board ) Violation Via (28.90708mm,0.57355m
求救ERC检测是出现的问题,
Violation Net VCM
Warning - net contains unplated pads
Violation Net CHR
Warning - net contains unplated pads
Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (On the board )
Violation Via (28.90708mm,0.57355mm) TopLayer to BottomLayer Actual Hole Size = 0mm
Arc (23.40409mm,-9.33843mm) TopLayer Actual Width = 0.25mm
Arc (43.11865mm,-11.50081mm) TopLayer Actual Width = 0.2mm
:Zero hole size via(s) detected
Via (28.90708mm,0.57355mm) TopLayer to BottomLayer on Net GND
Processing Rule :Broken-Net Constraint ( (On the board ) )
Violation Net FMANT
Warning - net contains unplated pads
Violation Net FL
Warning - net contains unplated pads

答案

hole size不为0时做出的PCB是有通孔的,如果为0则只是某一层的焊盘,没有孔